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1 ? fn8169.5 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. xdcp is a trademark of intersil americas inc. copyri ght intersil americas inc. 2005-2007. all rights reserved all other trademarks mentioned are the property of their respective owners. x9259 single supply/low power/256-tap/2-wire bus quad digitally-controlled (xdcp?) potentiometers the x9259 integrates four digi tally controlled potentiometers (xdcp) on a monolithic cmos integrated circuit. the digitally controlled potenti ometers are implemented with a combination of resistor elements and cmos switches. the position of the wipers are contro lled by the user through the 2-wire bus interface. each potentiometer has associated with it a volatile wiper coun ter register (wcr) and four non-volatile data registers that can be directly written to and read by the user. the conten t of the wcr controls the position of the wiper. at power-up, the device recalls the content of the default data r egisters of each dcp (dr00, dr10, dr20, and dr30) to the corresponding wcr. the xdcp can be used as a three-terminal potentiometer or as a two terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. features ? four separate potentiometers in one package ? 256 resistor taps?0.4% resolution ? 2-wire serial interfac e for write, read, and transfer operations of the potentiometer ? wiper resistance: 100 typical @ v cc = 5v ? 4 non-volatile data registers for each potentiometer ? non-volatile storage of multiple wiper positions ? standby current <5a max ?v cc : 2.7v to 5.5v operation ?50k , 100k versions of total resistance ? endurance: 100,000 data changes per bit per register ? 100 year data retention ? single supply version of x9258 ? 24 ld soic, 24 ld tssop ? low power cmos ? pb-free plus anneal available (rohs compliant) functional diagram power up, interface control and v cc v ss 2-wire r h0 r l0 dcp0 r w0 a1 sda scl a3 a2 wp wcr0 dr00 dr01 dr02 dr03 r h1 r l1 dcp1 r w1 wcr1 dr10 dr11 dr12 dr13 r h2 r l2 dcp2 r w2 wcr2 dr20 dr21 dr22 dr23 r h3 r l3 dcp3 r w3 wcr3 dr30 dr31 dr32 dr33 a0 interface status data sheet april 13, 2007
2 fn8169.5 april 13, 2007 ordering information part number part marking v cc limits (v) r total (k ) temperature range (c) package pkg. dwg. # x9259ts24 x9259ts 5 10% 100 0 to +70 24 ld soic m24.3 x9259ts24z (note) x9259ts z 0 to +70 24 ld soic (pb-free) m24.3 x9259ts24i x9259ts i -40 to +85 24 ld soic m24.3 x9259ts24iz (note) x9259ts zi -40 to +85 24 ld soic (pb-free) m24.3 x9259tv24i x9259tv i -40 to +85 24 ld tssop mdp0044 x9259tv24iz (note) x9259tv zi -40 to +85 24 ld tssop (pb-free) mdp0044 X9259US24* x9259us 50 0 to +70 24 ld soic m24.3 X9259US24z* (note) x9259us z 0 to +70 24 ld soic (pb-free) m24.3 X9259US24i x9259us i -40 to +85 24 ld soic m24.3 X9259US24iz (note) x9259us zi -40 to +85 24 ld soic (pb-free) m24.3 x9259uv24i* x9259uv i -40 to +85 24 ld tssop mdp0044 x9259uv24iz* (note) x9259uv z i -40 to +85 24 ld tssop (pb-free) mdp0044 x9259ts24-2.7* x9259ts f 2.7 to 5.5 100 0 to +70 24 ld soic m24.3 x9259ts24z-2.7* (note) x9259ts zf 0 to +70 24 ld soic (pb-free) m24.3 x9259ts24i-2.7 x9259ts g -40 to +85 24 ld soic m24.3 x9259ts24iz-2.7 (note) x9259ts zg -40 to +85 24 ld soic (pb-free) m24.3 x9259tv24-2.7 x9259tv f 0 to +70 24 ld tssop mdp0044 x9259tv24z-2.7 (note) x9259tv zf 0 to +70 24 ld tssop (pb-free) mdp0044 X9259US24-2.7 x9259us f 50 0 to +70 24 ld soic m24.3 X9259US24z-2.7 (note) x9259us zf 0 to +70 24 ld soic (pb-free) m24.3 X9259US24i-2.7 x9259us g -40 to +85 24 ld soic m24.3 X9259US24iz-2.7 (note) x9259us zg -40 to +85 24 ld soic (pb-free) m24.3 x9259uv24-2.7* x9259uv f 0 to +70 24 ld tssop mdp0044 x9259uv24z-2.7 (note) x9259uv zf 0 to +70 24 ld tssop (pb-free) mdp0044 x9259uv24i-2.7* x9259uv g -40 to +85 24 ld tssop mdp0044 x9259uv24iz-2.7* (note) x9259uv zg -40 to +85 24 ld tssop (pb-free) mdp0044 note: intersil pb-free plus anneal products em ploy special pb-free material sets; molding compounds/die attach materials and 100 % matte tin plate termination finish, which are rohs compliant and compatib le with both snpb and pb-free soldering operations. intersil pb- free products are msl classified at pb-free peak reflow tem peratures that meet or exceed the pb-free requirements of ipc/jedec j std-020. *add "t1" suffix for tape and reel. x9259
3 fn8169.5 april 13, 2007 circuit level applications ? vary the gain of a voltage amplifier ? provide programmable dc reference voltages for comparators and detectors ? control the volume in audio circuits ? trim out the offset voltage error in a voltage amplifier circuit ? set the output voltag e of a voltage regulator ? trim the resistance in wheatstone bridge circuits ? control the gain, characteristic frequency and q-factor in filter circuits ? set the scale factor and zero point in sensor signal conditioning circuits ? vary the frequency and duty cycle of timer ics ? vary the dc biasing of a pin diode attenuator in rf circuits ? provide a control variable (i, v, or r) in feedback circuits system level applications ? adjust the contrast in lcd displays ? control the power level of led transmitters in communication systems ? set and regulate the dc biasing point in an rf power amplifier in wireless systems ? control the gain in audio and home entertainment systems ? provide the variable dc bias for tuners in rf wireless systems ? set the operating points in temperature control systems ? control the operating point for sensors in industrial systems ? trim offset and gain errors in artificial intelligent systems pin configuration pin assignments pin (soic/ tssop) symbol function 2 a0 device address for 2-wire bus. (see note 1) 3r w3 wiper terminal of dcp3 4r h3 high terminal of dcp3 5r l3 low terminal of dcp3 6 nc1 must be left unconnected 7v cc system supply voltage 8r l0 low terminal of dcp0 9r h0 high terminal of dcp0 10 r w0 wiper terminal of dcp0 11 a2 device address for 2-wire bus. (see note 1) 12 wp hardware write protect ? active low 13 sda serial data input/output for 2-wire bus. 14 a1 device address for 2-wire bus. (see note 1) 15 r l1 low terminal of dcp1 16 r h1 high terminal of dcp1 17 r w1 wiper terminal of dcp1 18 v ss system ground 20 r w2 wiper terminal of dcp2 21 r h2 high terminal of dcp2 22 r l2 low terminal of dcp2 23 scl serial clock for 2-wire bus. 24 a3 device address for 2-wire bus. (see note 1) 6, 19 nc no connect 1 dnc do not connect note 1: a0 through a3 device address pins must be tied to a logic level. dnc a0 r w3 nc v cc r l0 1 2 3 4 5 6 7 8 9 10 24 23 22 21 20 19 18 17 16 15 a3 scl r l2 r h2 r w2 nc v ss r w1 r h1 r l1 soic/tssop x9259 r h3 14 13 11 12 r l3 r h0 r w0 a2 a1 sda wp x9259
4 fn8169.5 april 13, 2007 pin descriptions bus interface pins serial data input/output (sda) the sda is a bidirectional serial data input/output pin for a 2- wire slave device and is used to transfer data into and out of the device. it receives device address, opcode, wiper register address and data sent from a 2-wire master at the rising edge of the serial clock scl, and it shifts out data after each falling edge of the serial clock scl. it is an open drain output and may be wire-ored with any number of open drain or open collector outputs. an open drain output requires the use of a pull-up resistor. serial clock (scl) this input is used by 2-wire master to supply 2-wire serial clock to the x9259. device address (a3 through a0) the address inputs are used to set the least significant 4 bits of the 8-bit slave address. a match in the slave address serial data stream must be made with the address input in order to initiate communication with the x9259. a maximum of 16 devices may occupy the 2-wire serial bus. device pins a3 through a0 must be tied to a logic level which specifies the external address of the device, see figures 3, 4, and 5. potentiometer pins r h , r l the r h and r l pins are equivalent to the terminal connections on a mechanical potentiometer. since there are 4 potentiometers, there are 4 sets of r h and r l such that r h0 and r l0 are the terminals of dcp0 and so on. r w the wiper pin are equivalent to the wiper terminal of a mechanical potentiometer. sinc e there are 4 potentiometers, there are 4 sets of r w such that r w0 is the terminal of dcp0 and so on. bias supply pins system supply voltage (v cc ) and supply ground (v ss ) the v cc pin is the system supply voltage. the v ss pin is the system ground. other pins no connect no connect pins should be left open. this pins are used for intersil manufacturing and testing purposes. hardware write protect input (wp ) the wp pin when low prevents non-volatile writes to the data registers. serial data path from interface circuitry dr#0 serial bus input parallel bus input counter register inc/dec logic up/dn clk modified sck up/dn 8 8 counter if wcr = 00[h] then r w is closest to r l if wcr = ff[h] then r w is closest to r h wiper (wcr#) #: 0, 1, 2, or 3 one of four potentiometers dr#2 dr#1 dr#3 - - - decode dcp core r w r h r l figure 1. detailed pote ntiometer block diagram x9259
5 fn8169.5 april 13, 2007 principles of operation the x9259 is an integrated ci rcuit incorporating four dcps and their associated registers and counters, and the serial interface providing direct communication between a host and the potentiometers. dcp description each dcp is implemented with a combination of resistor elements and cmos switches. the physical ends of each dcp are equivalent to the fixed terminals of a mechanical potentiometer (r h and r l pins). the rw pin is an intermediate node, equivalent to the wiper terminal of a mechanical potentiometer. the position of the wiper terminal within the dcp is controlled by an 8-bit volatile wiper counter register (wcr). power up and down recommendations there are no restrictions on the power-up or power-down conditions of v cc and the voltages applied to the potentiometer pins provided that v cc is always more positive than or equal to v h , v l , and v w , i.e., v cc v h , v l , v w . the v cc ramp rate specification is always in effect. wiper counter register (wcr) the x9259 contains four wipe r counter registers, one for each potentiometer. the wiper counter register can be envisioned as a 8-bit parallel and serial load counter with its outputs decoded to select one of 256 wiper positions along its resistor array. the contents of the wcr can be altered in four ways: it may be written directly by the host via the write wiper counter register instruction (serial load); it may be written indirectly by transferring the contents of one of four associated data registers via the xfr data register instruction (parallel load); it can be modified one step at a time by the increment/decrement instruction (see instruction section for more details). finally, it is loaded with the contents of its data register zero (dr#0) upon power-up. (see figure 1) the wiper counter register is a volatile register; that is, its contents are lost when the x9259 is powered-down. although the register is autom atically loaded with the value in dr#0 upon power-up, this may be different from the value present at power-down. power-up guidelines are recommended to ensure proper loadings of the dr#0 value into the wcr# (see design considerations section). data registers (dr) each of the four dcps has four 8-bit non-volatile data registers. these can be read or written directly by the host. data can also be transferred between any of the four data registers and the associated wiper counter register. all operations changing data in one of the data registers is a non-volatile operation and takes a maximum of 10ms. if the application does not r equire storage of multiple settings for the potentiometer, the data registers can be used as regular memory locati ons for system parameters or user preference data. bit [7:0] are used to store one of the 256 wiper positions (0 ~ 255). table 1. wiper counter register, wcr (8-bit), wcr[7:0]: used to store the current wiper position (volatile). table 2. data register, dr (8-bit), bit [7:0]: used to store wiper positions or data (non-volatile). wcr7 wcr6 wcr5 wcr4 wcr3 wcr2 wcr1 wcr0 (msb) (lsb) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (msb) (lsb) x9259
6 fn8169.5 april 13, 2007 serial interface the x9259 supports a bidirect ional bus oriented protocol. the protocol defines any devic e that sends data onto the bus as a transmitter and the receiving device as the receiver. the device controlling the transfer is a master and the device being controlled is the slave. the master always initiates data transfers and provide the clock for both transmit and receive operat ions. therefore, the x9259 operates as a slave device in all applications. all 2-wire interface operations must begin with a start, followed by an identification byte, that selects the x9259. all communication over the 2-wire interface is conducted by sending the msb of each byte of data first. clock and data conventions data states on the sda line can change only during scl low periods. sda state cha nges during scl high are reserved for indicating start and stop conditions. see figure 2. on power up of the x9259 the sda pin is in the input mode. start condition all commands to the x9259 are preceded by the start condition, which is a high to low transition of sda while scl is high. the x9259 continuously monitors the sda and scl lines for the start condition and does not respond to any command until this condition is met. see figure 2. stop condition all communications must be terminated by a stop condition, which is a low to high transition of sda while scl is high. see figure 2. the stop condition is also used to place the device into the standby power mode after a read sequence. a stop condition can only be issued after the transmitting device has released the bus. acknowledge an ack, acknowledge, is a software convention used to indicate a successful data transfer. the transmitting device, either master or slave, releases the sda bus after transmitting eight bits. during the ninth clock cycle, the receiver pulls the sda line low to acknowledge the reception of the eight bits of data. see figure 3. the x9259 responds with an ack after recognition of a start condition followed by a valid identification byte, and once again after successful rece ipt of an instruction byte. the x9259 also responds with an ack after receiving a data byte after a write instruction. a valid identification byte cont ains the device type identifier 0101, as the four msbs, and the device address bits matching the logic states of pins a3, a2, a1, and a0, as the four lsbs. see figure 4. in the read mode, the device transmits eight bits of data, releases the sda line, and then monitors the line for an ack. the device continues transmitting data if an ack is detected. the device terminates further data transmissions if an ack is not detected. the master must then issue a stop condition to place the device into a known state. during the internal non-volatile write operation, the x9259 ignores the inputs at sda and scl, and does not issue an ack after identification bytes. x9259
7 fn8169.5 april 13, 2007 identification byte the first byte sent to the x9259 from the host is called the identification byte. the most significant four bits are a device type identifier, id[3:0] bits, which must be 0101. refer to table 3. only the device which slave address matches the incoming device address sent by the mast er executes the instruction. the a3 - a0 inputs can be actively driven by cmos input signals or tied to v cc or v ss . instruction byte (i) the next byte sent to the x925 9 contains the instruction and register pointer information. the four most significant bits are used provide the instruction opcode i [3:0]. the rb and ra bits point to one of the four data registers of each associated xdcp. the least two significant bits point to one of four wiper counter registers or dcps. the format is shown in table 4. data register selection #: 0, 1, 2, or 3 the least significant four bits of the identification byte are the slave address bits, ad[3:0]. to access the x9259, these four bits must match the logic values of pins a3, a2, a1, and a0. sda scl start data data stop stable change data stable figure 2. valid data changes, start, and stop conditions sda output from transmitter sda output from receiver 8 1 9 start ack scl from master figure 3. acknowledge response from receiver register rb ra dr#0 0 0 dr#1 0 1 dr#2 1 0 dr#3 1 1 x9259
8 fn8169.5 april 13, 2007 table 3. identification byte format table 4. instruction byte format note: 1/0 = data is one or zero id3 id2 id1 id0 a3 a2 a1 a0 0 1 0 1 logic value of pins a3, a2, a1, and a0 (msb) (lsb) device type identifier slave address i3 i2 i1 i0 rb ra p1 p0 (msb) (lsb) instruction register dcp selection opcode selection (wcr selection) table 5. instruction set instruction instruction set operation i3 i2 i1 i0 rb ra p1 p0 read wiper counter register 1 0 0 1 0 0 1/0 1/0 read the contents of the wiper counter register pointed to by p1 - p0 write wiper counter register 1 0 1 0 0 0 1/0 1/0 write new value to the wiper counter register pointed to by p1 - p0 read data register 1 0 1 1 1/0 1/0 1/0 1/0 read the contents of the data register pointed to by p1 - p0 and rb - ra write data register 1 1 0 0 1/0 1/0 1/0 1/0 write new value to the data register pointed to by p1 - p0 and rb - ra xfr data register to wiper counter register 1 1 0 1 1/0 1/0 1/0 1/0 transfer the contents of the data register pointed to by p1 - p0 and rb - ra to its associated wiper counter register xfr wiper counter register to data register 1 1 1 0 1/0 1/0 1/0 1/0 transfer the contents of the wiper counter register pointed to by p1 - p0 to the data register pointed to by rb - ra global xfr data registers to wiper counter registers 0 0 0 1 1/0 1/0 0 0 transfer the contents of the data registers pointed to by rb - ra of all four pots to their respective wiper counter registers global xfr wiper counter registers to data register 1 0 0 0 1/0 1/0 0 0 transfer the contents of both wiper counter registers to their respective data registers pointed to by rb - ra of all four dcps increment/decrement wiper counter register 0 0 1 0 0 0 1/0 1/0 enable increment/decrement of the control latch pointed to by p1 - p0 x9259
9 fn8169.5 april 13, 2007 instructions four of the nine instructions are three bytes in length. these instructions are: ? read wiper counter register ? read the current wiper position of the selected potentiometer, ? write wiper counter register ? change current wiper position of the selected potentiometer, ? read data register ? read the contents of the selected data register; ? write data register ? write a new value to the selected data register. the basic sequence of the three byte instructions is illustrated in figure 5. these three-byte instructions exchange data between the wcr and one of the data registers. a transfer from a data register to a wcr is essentially a write to a static ram, with the static ram controlling the wiper position. the response of the wiper to this action is delayed by t wrl . a transfer from the wcr (current wiper position), to a data register is a write to non- volatile memory and takes a minimum of t wr to complete. the transfer can occur between one of the four potentiometer?s wcr, and one of its associated registers, drs; or it may occur globally, where the transfer occurs between all potentiometers and one associated register. four instructions require a two-byte sequence to complete. these instructions transfer da ta between the host and the x9259; either between the host an d one of the data registers or directly between the host and the wiper counter register. these instructions are: ? xfr data register to wiper counter register ? this transfers the contents of one specified data register to the associated wiper counter register. ? xfr wiper counter register to data register ? this transfers the contents of the specified wiper counter register to the specified associated data register. ? global xfr data regist er to wiper counter register ? this transfers the contents of all specified data registers to the associated wiper counter registers. ? global xfr wiper counter register to data register ? this transfers the contents of all wiper counter registers to the specified associated data registers. increment/decrement command the final command is increment/decrement (figure 6 and 7). the increment/decrement command is different from the other commands. once the command is issued and the x9259 has responded with an acknowledge, the master can clock the selected wiper up and/or down in one segment steps; thereby, providing a fine tuning capability to the host. for each scl clock pulse (t high ) while sda is high, the selected wiper moves one wiper position towards the r h terminal. similarly, for each scl clock pulse while sda is low, the selected wiper moves one resistor wiper position towards the r l terminal. see instruction format for more details. s t a r t 0101 a2 a0 a c k i2 i1 i0 rb ra p1 a c k scl sda s t o p id3 id2 id1 id0 p0 device id external instruction opcode address register address dcp/wcr address a1 a3 i3 figure 4. two-byte instruction sequence i3 i2 i1 i0 rb ra id3 id2 id1 id0 device id external instruction opcode address register address pot/wcr address data for wcr[7:0] or dr[7:0] s t a r t 0101 a2 a1 a0 a c k p1 p0 a c k scl sda s t o p a c k d7 d6 d5 d4 d3 d2 d1 d0 a3 figure 5. three-byte instruction sequence 2-wire interface x9259
10 fn8169.5 april 13, 2007 i3 i2 i1 i0 id3 id2 id1 id0 device id external instruction opcode address register address pot/wcr address s t a r t 0101 a2 a1 a0 a c k ra p1 p0 a c k scl sda s t o p i n c 1 i n c 2 i n c n d e c 1 d e c n rb a3 figure 6. increment/decrement inst ruction sequence 2-wire interface scl sda r w inc/dec cmd issued voltage out t wrid figure 7. increment/decrement timing spec x9259
11 fn8169.5 april 13, 2007 instruction format read wiper counter register (wcr) write wiper counter register (wcr) read data register (dr) write data register (dr) global xfr data register (dr) to wiper counter register (wcr) notes: (1) ?mack?/?sack?: stands for the acknowledge sent by the master/slave. (2) ?a3 ~ a0?: stands for the device addresses sent by the master. (3) ?x?: indicates that it is a ?0? for testing pur pose but physically it is a ?don?t care? condition. (4) ?i?: stands for the increment operation, sda held high during acti ve scl phase (high). (5) ?d?: stands for the decrement operation, sda held low during active scl phase (high). s t a r t device type identifier device addresses s a c k instruction opcode dr/wcr addresses s a c k wiper position (sent by x9259 on sda) m a c k s t o p 0101a3a2a1a0 100100p1 p0 w c r 7 w c r 6 w c r 5 w c r 4 w c r 3 w c r 2 w c r 1 w c r 0 s t a r t device type identifier device addresses s a c k instruction opcode dr/wcr addresses s a c k wiper position (sent by master on sda) s a c k s t o p 0101a3a2a1a0 101000p1 p0 w c r 7 w c r 6 w c r 5 w c r 4 w c r 3 w c r 2 w c r 1 w c r 0 s t a r t device type identifier device addresses s a c k instruction opcode dr/wcr addresses s a c k wiper position (sent by x9259 on sda) m a c k s t o p 0 1 0 1a3a2a1a0 1011rbrap1 p0 w c r 7 w c r 6 w c r 5 w c r 4 w c r 3 w c r 2 w c r 1 w c r 0 s t a r t device type identifier device addresses s a c k instruction opcode dr/wcr addresses s a c k wiper position (sent by master on sda) s a c k s t o p high-voltage write cycle 0101a3a2a1a0 1100rbrap1 p0 w c r 7 w c r 6 w c r 5 w c r 4 w c r 3 w c r 2 w c r 1 w c r 0 s t a r t device type identifier device addresses s a c k instruction opcode dr/wcr addresses s a c k s t o p 0 1 0 1 a3 a2 a1 a0 0 0 0 1 rb ra 0 0 x9259
12 fn8169.5 april 13, 2007 global xfr wiper counter register (wcr) to data register (dr) transfer wiper counter register (wcr) to data register (dr) transfer data register (dr) to wiper counter register (wcr) increment/decrement wiper counter register (wcr) notes: (1) ?mack?/?sack?: stands for the acknowledge sent by the master/slave. (2) ?a3 ~ a0?: stands for the device addresses sent by the master. (3) ?x?: indicates that it is a ?0? for testing pur pose but physically it is a ?don?t care? condition. (4) ?i?: stands for the increment operation, sda held high during acti ve scl phase (high). (5) ?d?: stands for the decrement operation, sda held low during active scl phase (high). s t a r t device type identifier device addresses s a c k instruction opcode dr/wcr addresses s a c k s t o p high-voltage write cycle 0 1 0 1a3a2a1a0 1000rbra0 0 s t a r t device type identifier device addresses s a c k instruction opcode dr/wcr addresses s a c k s t o p high-voltage write cycle 0 1 0 1a3a2a1a0 1110rbrap1 p0 s t a r t device type identifier device addresses s a c k instruction opcode dr/wcr addresses s a c k s t o p 0 1 0 1 a3 a2 a1 a0 1 1 0 1 rb ra p1 p0 s t a r t device type identifier device addresses s a c k instruction opcode dr/wcr addresses s a c k increment/decrement (sent by master on sda) s t o p 0101a3a2a1a0 001000 p1 p0 i/di/d. . . .i/di/d x9259
13 fn8169.5 april 13, 2007 notes: 1. absolute linearity is utilized to determine actual wiper volt age versus expected voltage as determined by wiper position when used as a potentiometer. 2. relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. it is a measure of the error in step size. 3. mi = rtot / 255 or (r h ? r l ) / 255, single pot 4. during power up v cc > v h , v l , and v w . 5. n = 0, 1, 2, ?,255; m =0, 1, 2, ?, 254. absolute maximum ratings recommended operating conditions temperature under bias . . . . . . . . . . . . . . . . . . . . . .-65 c to +135 c storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65 c to +150 c voltage on scl, sda, any address input, v cc with respect to v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1v to +7v v = | (v h ?v l ) | . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5v lead temperature (soldering, 10 seconds) . . . . . . . . . . . . . . . 300 c i w (10 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6ma temperature (commercial) . . . . . . . . . . . . . . . . . . . . . 0c to +70c temperature (industrial). . . . . . . . . . . . . . . . . . . . . . .-40c to +85c supply voltage (v cc ) (note 4) limits x9259. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5v 10% x9259-2.7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7v to 5.5v wiper current ...........................................................................3ma power rating (each pot) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50mw caution: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stres s rating only; the functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. analog specifications over recommended industrial (2.7v) operat ing conditions unles s otherwise stated. symbol parameter test conditions limits min typ max units r total end to end resistance t version 100 k r total end to end resistance u version 50 k end to end resistance tolerance 20 % r w wiper resistance i w = @ v cc = 3v 300 i w = @ v cc = 5v 220 v term voltage on any r h or r l pin v ss = 0v v ss v cc v noise (note 6) ref: 1v -120 db / hz resolution 0.4 % absolute linearity (note 1) r w(n)(actual) - r w(n)(expected) (note 5) -1 +1 mi (note 3) relative linearity (note 2) r w(n + 1) - [r w(n) + mi ] (note 5) -0.6 +0.6 mi (note 3) temperature coefficient of r total (note 6) 300 ppm/ c ratiometric temp. coefficient (note 6) 20 ppm/c c h /c l /c w potentiometer capacitances (note 6) see macro model 10/10/25 pf v(v cc ) r total v(v cc ) r total x9259
14 fn8169.5 april 13, 2007 notes: 6. this parameter is not 100% tested 7. t pur and t puw are the delays required from the time the power supply (v cc ) is stable until the specific instruction can be issued. these parameters are periodically sampled and not 100% tested. dc electrical specifications over the recommended operating condi tions unless otherwise specified. symbol parameter test conditions limits min typ max units i cc1 v cc supply current (active) f scl = 400khz; v cc = +6v; sda = open; (for 2-wire, active, read and volatile write states only) 3ma i cc2 v cc supply current (non-volatile write) f scl = 400khz; v cc = +6v; sda = open; (for 2-wire, active, non-volatile write state only) 5ma i sb v cc current (standby) v cc = +6v; v in = v ss or v cc ; sda = v cc ; (for 2-wire, standby state only) 5 a i li input leakage current v in = v ss to v cc 10 a i lo output leakage current v out = v ss to v cc 10 a v ih input high voltage v cc x 0.7 v v il input low voltage v cc x 0.3 v v ol output low voltage i ol = 3ma 0.4 v v oh output high voltage i oh = -1ma, v cc +3v v cc - 0.8 v v oh output high voltage i oh = -0.4ma, v cc +3v v cc - 0.4 v endurance and data retention parameter min units minimum endurance 100,000 data changes per bit per register data retention 100 years capacitance symbol test max units test conditions c in/out (note 6) input / output capacitance (sda) 8 pf v out = 0v c in (note 6) input capacitance (scl, wp , a2, a1 and a0) 6 pf v in = 0v power-up timing symbol parameter min max units tr vcc (note 6) v cc power-up rate 0.2 v/ms tpur (note 7) power-up to initiation of read operation 1 ms tpuw (note 7) power-up to initiation of write operation 50 ms a.c. test conditions input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10ns input and output timing level v cc x 0.5 x9259
15 fn8169.5 april 13, 2007 equivalent a.c. load circuit 5v 1533 100pf sda pin r h 10pf c l c l r w r total c w 25pf 10pf r l spice macromodel ac timing symbol parameter min max units f scl clock frequency 400 khz t cyc clock cycle time 2500 ns t high clock high time 600 ns t low clock low time 1300 ns t su:sta start setup time 600 ns t hd:sta start hold time 600 ns t su:sto stop setup time 600 ns t su:dat sda data input setup time 100 ns t hd:dat sda data input hold time 30 ns t r scl and sda rise time 300 ns t f scl and sda fall time 300 ns t aa scl low to sda data output valid time 0.9 s t dh sda data output hold time 0 ns t i noise suppression time constant at scl and sda inputs 50 ns t buf bus free time (prior to any transmission) 1200 ns t su:wpa a0, a1 setup time 0 ns t hd:wpa a0, a1 hold time 0 ns high-voltage write cycle timing symbol parameter typ max units t wr high-voltage write cycle time (store instructions) 5 10 ms xdcp timing symbol parameter min max units t wrpo wiper response time after the third (last) power supply is stable 5 10 s t wrl wiper response time after instructi on issued (all load instructions) 5 10 s x9259
16 fn8169.5 april 13, 2007 symbol table . timing diagrams start and stop timing input timing output timing waveform inputs outputs must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low don?t care: changes allowed changing: state not known n/a center line is high impedance t su:sta t hd:sta t su:sto scl sda t r (start) (stop) t f t r t f scl sda t high t low t cyc t hd:dat t su:dat t buf scl sda t dh t aa x9259
17 fn8169.5 april 13, 2007 xdcp timing (for all load instructions) write protect and device address pins timing scl sda vwx (stop) lsb t wrl sda scl ... ... ... wp a0, a1 t su:wpa t hd:wpa (start) (stop) (any instruction) x9259
18 fn8169.5 april 13, 2007 applications information basic configurations of electronic potentiometers application circuits v r rw +v r i three terminal potentiometer; variable voltage divider two terminal variable resistor; variable current non inverting amplifie r voltage regulator offset voltage adjustment comparator with hysteresis + ? v s v o r 2 r 1 v o = (1+r 2 /r 1 )v s r 1 r 2 i adj v o (reg) = 1.25v (1+r 2 /r 1 )+i adj r 2 v o (reg) v in 317 + ? v s v o r 2 r 1 v ul = {r 1 /(r 1 +r 2 )} v o (max) rl l = {r 1 /(r 1 +r 2 )} v o (min) 100k 10k 10k 10k -12v +12v tl072 + ? v s v o r 2 r 1 } } x9259
19 fn8169.5 april 13, 2007 application circuits (continued) attenuator filter inverting amplifier equivalent l-r circuit + ? v s v o r 3 r 1 v o = g v s -1/2 g +1/2 g o = 1 + r 2 /r 1 fc = 1/(2 rc) + ? v s v o r 2 r 1 z in = r 2 + s r 2 (r 1 + r 3 ) c 1 = r 2 + s leq (r 1 + r 3 ) >> r 2 + ? v s function generator r 2 r 4 r 1 = r 2 = r 3 = r 4 = 10k + ? v s r 2 r 1 r c } } v o = g v s g = - r 2 /r 1 r 2 c 1 r 1 r 3 z in + ? r 2 + ? r 1 } } r a r b frequency r 1 , r 2 , c amplitude r a , r b c v o x9259
20 fn8169.5 april 13, 2007 x9259 small outline plast ic packages (soic) notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include in terlead flash or protrusions. inter- lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?b?, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. controlling dimension: millimete r. converted inch dimensions are not necessarily exact. index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 c h 0.25(0.010) b m m m24.3 (jedec ms-013-ad issue c) 24 lead wide body small outline plastic package symbol inches millimeters notes min max min max a 0.0926 0.1043 2.35 2.65 - a1 0.0040 0.0118 0.10 0.30 - b 0.013 0.020 0.33 0.51 9 c 0.0091 0.0125 0.23 0.32 - d 0.5985 0.6141 15.20 15.60 3 e 0.2914 0.2992 7.40 7.60 4 e 0.05 bsc 1.27 bsc - h 0.394 0.419 10.00 10.65 - h 0.010 0.029 0.25 0.75 5 l 0.016 0.050 0.40 1.27 6 n24 247 0 8 0 8 - rev. 1 4/06
21 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn8169.5 april 13, 2007 x9259 thin shrink small outline package family (tssop) n (n/2)+1 (n/2) top view a d 0.20 c 2x b a n/2 lead tips b e1 e 0.25 cab m 1 h pin #1 i.d. 0.05 e c 0.10 c n leads side view 0.10 cab m b c see detail ?x? end view detail x a2 0 - 8 gauge plane 0.25 l a1 a l1 seating plane mdp0044 thin shrink small outline package family symbol millimeters tolerance 14 ld 16 ld 20 ld 24 ld 28 ld a 1.20 1.20 1.20 1.20 1.20 max a1 0.10 0.10 0.10 0.10 0.10 0.05 a2 0.90 0.90 0.90 0.90 0.90 0.05 b 0.25 0.25 0.25 0.25 0.25 +0.05/-0.06 c 0.15 0.15 0.15 0.15 0.15 +0.05/-0.06 d 5.00 5.00 6.50 7.80 9.70 0.10 e 6.40 6.40 6.40 6.40 6.40 basic e1 4.40 4.40 4.40 4.40 4.40 0.10 e 0.65 0.65 0.65 0.65 0.65 basic l 0.60 0.60 0.60 0.60 0.60 0.15 l1 1.00 1.00 1.00 1.00 1.00 reference rev. f 2/07 notes: 1. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15mm per side. 2. dimension ?e1? does not include interlead flash or protrusions. interlead flash and protrusi ons shall not exceed 0.25mm per side. 3. dimensions ?d? and ?e1? are measured at datum plane h. 4. dimensioning and tolerancing per asme y14.5m - 1994.

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